When generating a module using the Xilinx CORE Generator for a Viewlogic schematic design, you may get the following error:
Error: Could not read symbol file c:\dsp_proj\regsub2\SYM\regsub2.1 java.io.FileNotFoundException: c:\dsp_proj\regsub2\SYM\regsub2.1 Error: Generating Viewsym Error: Errors Occurred during during the generation of regsub2 Error: Could not read symbol file c:\dsp_proj\regsub2\SYM\regsub2.1 java.io.FileNotFoundException: c:\dsp_proj\regsub2\SYM\regsub2.1 Error: Generating Viewsym Error: Errors Occurred during during the generation of regsub2
This error messge indicates that COREGEN had a problem generating the symbol for the Core Generator module.
In COREGEN, the Viewlogic symbol generation process involves several programs external to the native COREGEN application. These are called by a batch file on Windows95 and NT called VLLINK.BAT, and a script file called "vllink" (on UNIX). These programs call a Viewlogic utility call VHDL2SYM.EXE (vhdl2sym), which takes a VHDL port list as input, and generates a symbol from it.
The "Could not read symbol" error indicates that something has gone wrong during the symbol generation process.
Before generating the Coregen module, be sure you have set the path and alias correctly for your design directory in the Workview Office Project Manager. The alias for the directory in which you generate the Core should be "coregen" or "primary".
Be sure to check that the spelling of the alias, "coregen", is correct, and that it matches the setting for "Symbol Library" in the Core Generator under the
Options ->System Options
After saving the Project Manager with the correct library setting, re-run COREGEN.
For more information on doing Coregen designs using the Viewlogic Schematic Flow, see COREGEN -> Help -> Help Topics -> Viewlogic Schematic Flow.