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AR# 31829

LogiCORE DDS (Direct Digital Synthesizer) Compiler v2.1 - After a reset, why does the RDY signal go high a couple cycles prior to the sine and cosine outputs changing values?


After a reset to the DDS core, the RDY signal goes high two clock cycles before the output changes. Why?


This is due to a known issue with the RDY signal behavior. After a reset followed immediately by writing a new value to the phase increment register the RDY signal will go high two clock cycles early. If a reset is followed by the same value being written to the phase increment register as was previously loaded, the additional two cycles of latency will not be seen. 
This will be addressed in a future version of the DDS Compiler core.
AR# 31829
Date 05/21/2014
Status Archive
Type General Article
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