UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31850

Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for Device Control Register

Description

Known Issue: v1.12, v1.11, v1.10.1, v1.10, 1.9, 1.8, 1.7.1, 1.7, 1.6.1, 1.6, 1.5.2, 1.5.1, 1.5, 1.4, 1.3, 1.2, 1.1

The example simulation testbench writes to the Endpoint's Device Control Register. However, the register number written is incorrect. It writes address 60h instead of 68h.

Solution

For a description of the register space in the Endpoint Block Plus Core, see The Endpoint Block Plus User Guide (UG341); Chapter 2, PCI Configuration Space.

The Device Control Register is at address 68h.

To fix this:

Verilog File pci_exp_usrapp_tx.v

Find the task TSK_BAR_PROGRAM and change the last configuration write to be as follows:

TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h68, 32'h0000005f, 4'h1);

VHDL File test_interface.vhd

Find the procedure PROC_BAR_PROGRAM and change the last configuration write to be as follows:

PROC_TX_TYPE0_CONFIGURATION_WRITE (
DEFAULT_TAG, --tag :in std_logic_vector (7 downto 0);
X"068", --reg_addr 12'h68
X"0000005F", --reg_data : in std_logic_vector (31 downto 0);
X"1", --first_dw_be : in std_logic_vector (3 downto 0);
trn_td_c, trn_tsof_n,trn_teof_n,trn_trem_n_c, trn_tsrc_rdy_n, trn_lnk_up_n, trn_tdst_rdy_n, trn_clk);

Revision History

09/16/2009- Updated for ISE 11.3 and core version v1.12.
06/24/2009 - Updated for ISE 11.2 and core version v1.11
04/13/2009- Updated for ISE 11.1 and core version v1.10.
10/28/2008 - Initial Release.
AR# 31850
Date Created 10/28/2008
Last Updated 08/09/2010
Status Active
Type ??????
IP
  • Endpoint Block Plus Wrapper for PCI Express