Please be aware that some tri-speed PHYs can stop the MII TX CLK in 1G GMII mode, but this is not always the case. For example, the Marvell 88E1111 PHY on the ML40X/50X demo boards defaults to having the PHY output the MII TX CLK in 1G mode. Therefore, this issue does not occur in the default GMII configuration of these boards.
This issue only affects the Virtex-4 and Virtex-5 FPGA Embedded TEMAC when using the standard clocking for tri-speed GMII in the following cores:
This is not an issue in the following cases:
To work around the issue:
This issue is fixed in 11.1 for the Virtex-5 FPGA Embedded Tri-mode Ethernet MAC wrapper by using external clock muxes.
This issue is fixed in 12.1 for the Virtex-4 FPGA Embedded Tri-mode Ethernet MAC wrapperby using external clock muxes.