Where to find the Simultaneously Switching Noise (SSO/SSN) information depends on the device families.
For Virtex-6, SSN analysis is done in PlanAhead.
For all UltraScale and 7 Series families, the SSN is done in Vivado.
There are no SSO tables in the data sheet.
For Spartan-6 FPGAs, the information was available in both the data sheet and in the PlanAhead tool from software version 12.1 and beyond.
In the Spartan-6 FPGA Data Sheet, Table-33 provides the number of equivalent VCCO/GND pairs per bank. For each output signal standard and drive strength, Table 34 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank.
The guidelines are categorized by package style, slew rate, and output drive current. The number of SSOs are also specified by I/O bank. Multiply the appropriate numbers from each table to calculate the maximum number of SSOs allowed within an I/O bank.
In previous architectures such as Virtex-5, Virtex-4, Spartan-3, etc., the SSO information is available in the family user guide.
Supplementary SSO/SSN Answer Records:
The SSN noise reports the Margin Remaining. For an explanation of what margin means, see (Xilinx Answer 44394).
For an explanation of why Spartan-6 Simultaneously Switching Noise limits for a 12 mA and stronger driver are significantly lower than for an 8 mA driver, see (Xilinx Answer 34528).
For Spartan-6 SSO limits when using untuned settings, see (Xilinx Answer 43211).
For Spartan-6 MIG SSN Analysis, see (Xilinx Answer 36141).
For a detailed discussion about handling SSOs, refer to Xilinx XAPP689: "Managing Ground Bounce in Large FPGAs."
The SSO guidelines provided in the data sheets or PlanAhead can be used in conjunction with the methodology outlined in the application note.
For power bypassing/decoupling guidelines, refer to Xilinx XAPP623: "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors".
See also WP323 Signal Integrity: Tips and Tricks White Paper.