When I implement my System Generator for DSP design containing a FIR Compiler block, the following error occurs:
This error can occur in designs using the FIR Compiler block in System Generator for DSP, given the following conditions:
The FIR Compiler cannot currently support an architecture which optimizes a symmetric coefficient structure by folding the coefficients and using a pre-adder across multiple DSP48 columns.
This error can occur because System Generator for DSP does not check if the FIR Compiler configuration required exceeds the DSP48 slice column height on the device, and might generate a core which cannot be placed on the given device.
In some cases, turning on automatic multi-column support is required in order for filters to be automatically cascaded across multiple columns.
To work around this issue, you can either specify the coefficients as non-symmetric, or reduce the number of coefficients, or check to see if the multi-column support is set to automatic.
In the 11.2 release of System Generator for DSP, a more descriptive error message is given to explain the violation.