AR# 31985


10.1 PAR - "WARNING: Route:436 - Unroutable situation detected for Architecture Wizard PLL2DCM core"


An unroutable situation was detected when I used instantiation from 10.1 Architecture Wizard for PLL2DCM. The warning message is similar to the following:

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:

Unroutable signal: PLL2DCM_inst/CLKOUTDCM0_CLKIN pin: PLL2DCM_inst/DCM_ADV_INST/CLKIN
Unroutable signal: PLL2DCM_inst/CLKOUTDCM0_CLKIN pin: PLL2DCM_inst/FDS_Q_OUT/CLK
Unroutable signal: PLL2DCM_inst/CLKOUTDCM0_CLKIN pin: PLL2DCM_inst/FD3_Q_OUT/CLK
Unroutable signal: PLL2DCM_inst/CLKOUTDCM0_CLKIN pin: PLL2DCM_inst/FD1_Q_OUT/CLK


Architecture Wizard is creating reset logic for the DCM, which is sourced by PLL output clock CLKOUTDCM0_CLKIN driving FD and OR. However, it is not possible for the Clock to be routed out of the CMT when the dedicated DCM routing is used. This conflict leads to unroutable design.

To work around the issue, you need to instantiate PLL and DCM individually, and add the reset logics for the DCM manually using an inverter and a SRL16. See (Xilinx Answer 18181).

1. Tie the user reset to the PLL only.

2. Use the PLL CLKIN to clock the reset logic.

3. Drive the reset of the DCM with the inverted LOCKED signal of the PLL, including a SRL module that forces the reset to be held for at least three valid clock cycles of the DCM CLKIN.

This issue is scheduled to be fixed in ISE 11.1.

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AR# 31985
Date 01/25/2013
Status Active
Type General Article
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