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AR# 32001

Sim Libraries - "ERROR:HDLCompiler:841 - "%.vhd" Line %d. Expecting type std_logic_vector for <we>."


Keywords: Unimacro, HDLcompiler, 841, std_logic_vector, std_logic

Why does the following error occur when I run synthesis with BRAM Unimacro instantiated in HDL?

"ERROR:HDLCompiler:841 - "%.vhd" Line #. Expecting type std_logic_vector for <we>."


When WE is 1 bit wide, WE should be defined as std_logic_vector (0 downto 0) and not std_logic, since WE port in the UNIMACRO is defined as std_logic_vector.
AR# 32001
Date 12/17/2008
Status Active
Type General Article
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