AR# 32004


MIG v2.3, Virtex-5 DDR2 - Incorrect directed routing constraints for Virtex-5 TXT devices when center column banks are used


The Virtex-5 DDR2 SDRAM design specifically places capture scheme logic, as required by the algorithm, using directed routing constraints. These constraints are set in the ddr2_phy_dq_iob.v/.vhd file and through proper setting of specific top-level parameters. For detailed information on this design and the required placement, refer to Xilinx Application Note 858 and (Xilinx Answer 29313):

When a MIG design is generated targeting a Virtex-5 TXT device using center column banks, the directed routing constraints are incorrect. This causes a warning similar to the following during PAR:

INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 64
WARNING:ParHelpers:198 - One or more "EXACT" mode Directed Routing constrained net(s) were not successfully routed
according to the constraint(s). The router attempted to route the net(s) without regard to the constraint. The number
of nets found with Directed Routing Constraints: 64, number successfully routed using the constraints: 16, number
failed: 48. The failed nets are listed below. Please use FPGA Editor to determine the cause of the failure.
Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/stg1_out_fall_0s
Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/stg1_out_rise_0s
Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[8].u_iob_dq/stg1_out_rise_0m
Net u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[8].u_iob_dq/stg1_out_fall_0m


If you encounter this issue, please open a WebCase and Xilinx Technical Support will provide further assistance.

To open a WebCase, please go to:

AR# 32004
Date 12/15/2012
Status Active
Type General Article
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