The Virtex-5 DDR2 SDRAM design specifically places capture scheme logic, as required by the algorithm, using directed routing constraints. These constraints are set in the ddr2_phy_dq_iob.v/.vhd file and through proper setting of specific top-level parameters. For detailed information on this design and the required placement, refer to Xilinx Application Note 858 and (Xilinx Answer 29313):
When a MIG design is generated targeting a Virtex-5 TXT device using center column banks, the directed routing constraints are incorrect. This causes a warning similar to the following during PAR:
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 64
WARNING:ParHelpers:198 - One or more "EXACT" mode Directed Routing constrained net(s) were not successfully routed
according to the constraint(s). The router attempted to route the net(s) without regard to the constraint. The number
of nets found with Directed Routing Constraints: 64, number successfully routed using the constraints: 16, number
failed: 48. The failed nets are listed below. Please use FPGA Editor to determine the cause of the failure.
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