UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 32022: LogiCORE Serial RapidIO v5.1 - Snooper logic reports errors in simulation of x1 core

AR# 32022

LogiCORE Serial RapidIO v5.1 - Snooper logic reports errors in simulation of x1 core

Description

After running the SRIO core's example design simulation with a x1 core, the "rx.log" and "tx.log" files produced are not parsing packets correctly, and report numerous errors similar to the following: 

 

ERROR - Unexpected data for Ftype 2 transaction 

ERROR - Doorbell max size packet exceeded

Solution

This issue only affects the Snooper portion of the core's Example Design, and will be fixed in the v5.2 core.  

 

Revision History 

 

01/06/2009 - Initial Release

AR# 32022
Date 05/23/2014
Status Archive
Type General Article
Page Bookmarked