Support for the Virtex-6 FPGA System Monitor will be added in the 12.1 timeframe.
Can a customer use the Virtex-5 FPGA core?
Currently, CORE Generator does not support the System Monitor core for the Virtex-6 FPGA, but the System Monitor is a supported block.
The user can use the Virtex-5 FPGA System Monitor core in their Virtex-6 FPGA design.
To create the Virtex-5 FPGA System Monitor core, open CORE Generator standalone
Go to Start -> Programs -> Xilinx ISE Design Suite -> ISE -> Accessories -> CoreGen
Create a new CORE Generator project and select any Virtex-5 FPGA part
Ensure the All IP Versions check box is clicked
Expand FPGA Features and Design
Select System Monitor Wizard and customize as required
CORE Generator will generate HDL (.vhd, .v) that can be used to instantiate the System Monitor in the Virtex-6 FPGA design
See Xilinx Answer 24512 for Known issues with the System Monitor Wizard