In the file "xps_timer.vhd", lines 361 and 362, the signal assignments appear to be incorrect:
C_PLB_DWIDTH => C_SPLB_AWIDTH,
C_PLB_AWIDTH => C_SPLB_DWIDTH,
should be:
C_PLB_DWIDTH => C_SPLB_DWIDTH,
C_PLB_AWIDTH => C_SPLB_AWIDTH,
The signal assignments are incorrect and should be changed as shown above.
This problem is scheduled to be fixed in the 11.1 EDK toolset.
AR# 32055 | |
---|---|
Date | 05/23/2014 |
Status | Archive |
Type | General Article |