Is the synchronous reset input SCLR dependent upon clock enable CE?
The synchronous reset (SCLR) works correctly only if the clock enable (CE) signal, if selected, is asserted High.
Please see (Xilinx Answer 29448) for a detailed list of LogiCORE Viterbi Decoder Release Notes and Known Issues.
| AR# 32061 | |
|---|---|
| Date | 05/23/2014 |
| Status | Archive |
| Type | General Article |