UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 32061: LogiCORE Viterbi Decoder V6.2 - Is the synchronous reset input SCLR dependent upon clock enable CE?

AR# 32061

LogiCORE Viterbi Decoder V6.2 - Is the synchronous reset input SCLR dependent upon clock enable CE?

Description

Is the synchronous reset input SCLR dependent upon clock enable CE?

Solution

The synchronous reset (SCLR) works correctly only if the clock enable (CE) signal, if selected, is asserted High.  

 

Please see (Xilinx Answer 29448) for a detailed list of LogiCORE Viterbi Decoder Release Notes and Known Issues.

AR# 32061
Date 05/23/2014
Status Archive
Type General Article
Page Bookmarked