When I simulate my System Generator for DSP design, I receive the following error:
"illegal rate transition found. Sample time [1000000 0] of ... at input port1 is different from sample time [1 0] of its source ... at output port 1. A rate transition must be inserted between them"
However, the two blocks in questions should both be at the same rate. Why do I receive this error?
This error message can occur if you change the Simulation Configuration Parameters for the Simulink model from the default settings.
In the Simulink Configuration Parameters dialog (Simulation menu > Configuration Parameters (ctrl-E)) go to the Diagnostics > Sample Time page.
Here, set "Single task rate transition" to "none".
Because of the way System Generator interacts with Simulink blocks and schedules its own simulation, this setting must remain at "none".