UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32110

11.1 Release Note - Timing Analysis/trce - Why do I see some Component Switching Limits, such as pulse limits, that are larger than my PERIOD limit?

Description

Keywords: TRCE, TWX, TRACE, pin limit,

Why do I see some Component Switching Limits, such as pulse limits, that are larger than my PERIOD limit?

This is what I am seeing in the output of TRCE (TWR):
MINPERIOD 2.222ns
MINLOWPULSE 2ns
MINHIGHPULSE 2.5ns

The Period is declared to be 2.222 ns, but from the pulse limits the fastest the clock could actually run at is 2 ns (MINLOWPULSE) + 2.5 ns (MINHIGHPULSE) = 4.5 ns, not 2.222 ns.

Solution

When the Timing Tools perform checks on the Period and Pulse Limits, they may check against the same or different components. Once the most limiting requirement is identified, it will be reported.

It is counter-intuitive to see a Minimum Period limit smaller than the Minimum High Pulse limit. However, there is something in the clock path or one of the components this clock is driving, which is limiting the clock to have at a minimum a Period of 2.222 ns. There is also something in this path that requires that the Minimum High Pulse be 2.5 ns.

All of the Component Switching Limits must be used met, so the most stringent limit (or combination of limits) is the true hardware limitation.

AR# 32110
Date Created 04/07/2009
Last Updated 04/10/2009
Status Active
Type General Article