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AR# 32120

11.1 Release Notes - PAR/Timing Analyzer/trce - Why do I see Component Switching Limit warnings in my 11.1 PAR report?


Why do I see Component Switching Limit warnings in my 11.1 PAR report?

-In 10.1, my design had the following warnings:

WARNING:Timing:3238 - Timing Constraint

"TS_clk = PERIOD TIMEGRP "clk" 1 ns HIGH 50%;"

fails the pulse width check for clock "reset_IBUF" because the low value (500 ps) or high value (500 ps) is less

than the minimum internal pulse width limits of 527 ps low and 527 ps high on pin

"/top/PACKED/top/Tracking_Module/Tracking_Module\/address<3>/Tracking_Module\/address_0/SR". Please increase the

period of the constraint to remove this timing failure.

-Now, in 11.1, my design has the following:

WARNING:Par:450 - At least one timing constraint is impossible to meet because component switching limit violations have

been detected for a constrained component. A timing constraint summary below shows the failing constraints (preceded

with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files

to evaluate the component switching limit violations in more detail. Evaluate the data sheet for alternative

configurations for the component that could allow the frequencies requested in the constraint. Otherwise, the timing

constraint covering this component might need to be modified to satisfy the component switching limits specified in

the data sheet.

INFO:Timing:3284 - This timing report was generated using estimated delay

information. For accurate numbers, please refer to the post Place and Route

timing report.

Asterisk (*) preceding a constraint indicates it was not met.

This may be due to a setup or hold violation.


Constraint | Check | Worst Case | Best Case | Timing | Timing

| | Slack | Achievable | Errors | Score


* TS_clk = PERIOD TIMEGRP "clk" 1 ns HIGH 5 | SETUP | -1.782ns| 2.782ns| 147| 59989

0% | HOLD | 0.291ns| | 0| 0

| MINPERIOD | -0.818ns| 1.818ns| 2| 1636

| MINLOWPULSE | -0.054ns| 1.054ns| 11| 594

| MINHIGHPULSE| -0.054ns| 1.054ns| 11| 594


OFFSET = OUT 15 ns AFTER COMP "clk" | MAXDELAY | 6.891ns| 8.109ns| 0| 0


OFFSET = IN 10 ns BEFORE COMP "clk" | SETUP | 7.823ns| 2.177ns| 0| 0



Component Switching Limits are a new way of reporting the most limiting characteristics of clocks or other signals per constraint. These include hardware limitations. These are expected changes in the PAR report, and directly correlate to the use of constraints instead of reporting on the limitation of the hardware.
AR# 32120
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
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