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AR# 32133

LogiCORE IP Color Filter Array Interpolation (CFA) - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Color Filter Array Interpolation Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Color Filter Array Interpolation Lounge:
http://www.xilinx.com/products/ipcenter/EF-DI-CFA.htm

Solution

General LogiCORE IP Color Filter Array Interpolation Issues
LogiCORE IP Color Filter Array Interpolation v6.01.a
  • Initial release in ISE 14.3 and Vivado 2012.3 tools
Supported Devices (ISE)
  • All 7 series
  • All Virtex-6
  • All Spartan-6
Supported Devices (Vivado)
  • All 7 series
New Features
  • Fixed clock domain issues with registers in the AXI4-Lite connection
Resolved Issues (ISE)
  • (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Resolved Issues (Vivado)
  • (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Known Issues (ISE) Known Issues (Vivado)
LogiCORE IP Color Filter Array Interpolation v6.00.a
  • Initial release in ISE 14.2 and Vivado 2012.2 tools
Supported Devices (ISE)
  • All 7 series
  • All Virtex-6
  • All Spartan-6
Supported Devices (Vivado)
  • All 7 series
New Features
  • Separate clock domains between AXI4-Lite and AXI4-Stream
Bug Fixes
  • N/A
Known Issues (ISE)
  • (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?
Known Issues (Vivado)
  • (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
  • (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

LogiCORE IP Color Filter Array Interpolation v5.00.a
  • Initial release in ISE 14.1 and Vivado 2012.1 tools
Supported Devices (ISE)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6
Supported Devices (Vivado)
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
New Features
  • ISE 14.1 design tools support
  • AXI4-Stream data interfaces
  • Optional AXI4-Lite control interface
  • Built-in, optional bypass and test-pattern generator mode
  • Built-in, optional throughput monitors
  • Supports spatial resolutions from 128x128 up to 7680x7680
  • Supports 1080P60 in all supported device families
  • Supports 4kx2k @ 24 Hz in supported high performance devices
Bug Fixes
  • N/A
Known Issues
LogiCORE IP Color Filter Array Interpolation v4.0
  • Initial release in ISE Design Suite 13.3
Supported Devices
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA LX/LXT
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
  • Spartan-6 -1L XQ LX
New Features
  • ISE 13.3 design tools support
  • Virtex-7 and Kintex-7
  • AXI4-Lite bus interface support for the EDK Pcore interface
Bug Fixes
  • (Xilinx Answer 41725)Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model?
Known Issues
  • (Xilinx Answer 41589)Does the CFA affect the original Bayer pattern input data?
  • (Xilinx Answer 54069)Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pCore in XPS?

LogiCORE IP Color Filter Array Interpolation v3.0 New Features
  • EDK pCore driver software macros defined.
  • GPP and EDK interface behavior changed. When the user updates and commits new timing register values, unmodified registers inherit the latest values measured by the timing generator, instead of the GUI default parameters, which was the behavior in v1.0 and v2.0 of the core.
  • GUI tooltips, minimum and maximum values were updated.
  • Core Configurable in EDK
  • Bit 7 of the Status register reflects whether the timing generator is locked.
Bug Fixes
  • CR 553188 : GUI timing parameters available only for con
  • CR 553183 : Description of the Timing Parameters is not clear
  • (Xilinx Answer 38912)Why is VBLANK and HBLANK polarity wrong for the Constant Interface?
Known Issues
  • (Xilinx Answer 41589)Does the CFA affect the original Bayer pattern input data?
  • (Xilinx Answer 41725)Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model?
  • (Xilinx Answer 54069) Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pCore in XPS?

LogiCORE IP Color Filter Array Interpolation v2.0
  • Initial release in ISE Design Suite 12.2
New Features
  • Number of total columns and rows size increased to 4k x 4k pixels
  • Support for Spartan-6 and Virtex-6 devices added
  • Pcore support for the XSVI bus added
  • Linux 32 and 64-bit support
Bug Fixes
  • CR 553188 : GUI timing parameters available only for constant interface
  • CR 553183 : Description of the Timing Parameters is not clear
  • CR 527227 : GUI out of Range error generated by CFA core in CORE Generator
  • (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core"
Known Issues
LogiCORE IP Color Filter Array Interpolation v1.0
  • Initial release in ISE Design Suite 11.1
New Features
  • RGB and CMY Bayer image sensor support
  • 5x5 interpolation aperture
  • Low-footprint, high quality interpolation
  • Support for streaming or frame buffer processing
  • Selectable processor interface
    • EDK pCore
    • General Processor
    • Constant Interface
    • Transparent Interface
  • Configurable 8, 10, and 12-bit input and output
  • Automatic detection of timing parameters and timing signal polarities
  • ISE 11.1 design tools support
Bug Fixes
  • N/A
Known Issues
  • (Xilinx Answer 32340) Why does my Image Pipe Video IP core fail to update the netlist when the parameters or the license is changed, but the component name remains constant?
  • (Xilinx Answer 33581) Why is the output simulation netlist for my design encrypted, and only readable by the ISE tools simulator?
  • (Xilinx Answer 33872) "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
  • (Xilinx Answer 35130) Why do I get the following error when generating with a Design Linking License? ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
47455 LogiCORE IP Color Filter Array Interpolation v5.00.a - Why does the CFA fail if the image size is less than 128x128 pixels? N/A N/A
41726 LogiCORE IP Color Filter Array Interpolation v3.0 - Patch updates for Color Filter Array Interpolation N/A N/A
41725 LogiCORE IP Color Filter Array Interpolation v3.0 - Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model? N/A N/A
41589 LogiCORE IP Color Filter Array Interpolation (CFA) v3.0 and v4.0 - Does the CFA affect the original Bayer pattern input data? N/A N/A
38912 LogiCORE IP Color Filter Array Interpolation v2.0 - Why is VBLANK and HBLANK polarity wrong for the Constant Interface? N/A N/A
38830 LogiCORE IP Color Filter Array Interpolation v2.0 - Why are some of the detected values one less than expected? N/A N/A
36149 LogiCORE IP Color Filter Array Interpolation - When using the transparent or constant modes, does h_blank need to be asserted when v_blank is asserted? N/A N/A
34068 LogiCORE IP Color Filter Array Interpolation - What algorithm does the Xilinx Color Filter Array Interpolation use? N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
51483 ISE 14.2 / Vivado 2012.2 Video IP - Why does my Video IP lock up when a partial input frame is passed by the Video In To AXI-4 Stream input core? N/A N/A
51589 14.2 / 2012.2 Video IP - Why does the Video IP stop working (producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? N/A N/A
52215 14.3 / 2012.2 Video IP - Why does my core fail timing with a critical warning? N/A N/A
53876 LogiCORE IP Color Filter Array Interpolation (CFA) v6.01.a - Patch updates for Color Filter Array Interpolation N/A N/A
54069 LogiCORE IP Color Filter Array Interpolation (CFA) v3.0 and v4.0 - Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pcore in XPS? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41726 LogiCORE IP Color Filter Array Interpolation v3.0 - Patch updates for Color Filter Array Interpolation N/A N/A
41725 LogiCORE IP Color Filter Array Interpolation v3.0 - Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model? N/A N/A
41589 LogiCORE IP Color Filter Array Interpolation (CFA) v3.0 and v4.0 - Does the CFA affect the original Bayer pattern input data? N/A N/A
38912 LogiCORE IP Color Filter Array Interpolation v2.0 - Why is VBLANK and HBLANK polarity wrong for the Constant Interface? N/A N/A
38830 LogiCORE IP Color Filter Array Interpolation v2.0 - Why are some of the detected values one less than expected? N/A N/A
37987 Where can I find UG762, Xilinx Streaming Video Interface User Guide? N/A N/A
36149 LogiCORE IP Color Filter Array Interpolation - When using the transparent or constant modes, does h_blank need to be asserted when v_blank is asserted? N/A N/A
35130 LogiCORE IP Image Processing Pipeline Cores - The following error is received when generating with a Design Linking License: "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core" N/A N/A
34068 LogiCORE IP Color Filter Array Interpolation - What algorithm does the Xilinx Color Filter Array Interpolation use? N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
33581 LogiCORE Image Processing Pipeline v1.0 - Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator? N/A N/A
32340 11.1 CORE Generator - Why do my Image Processing Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant? N/A N/A
32136 LogiCORE IP Image Processing Pipeline - Release Notes and Known Issues N/A N/A
47455 LogiCORE IP Color Filter Array Interpolation v5.00.a - Why does the CFA fail if the image size is less than 128x128 pixels? N/A N/A
AR# 32133
Date Created 03/10/2009
Last Updated 01/31/2013
Status Active
Type Known Issues
IP
  • Color Filter Array Interpolation