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AR# 32135

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LogiCORE IP Gamma Correction - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Gamma Correction Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Gamma Correction core IP Page:


https://www.xilinx.com/products/intellectual-property/ef-di-gamma.html

Note: The LogiCORE IP Gamma Correction is in maintenance mode and not recommended for new designs.

Solution

General LogiCORE IP Gamma Correction Issues

LogiCORE IP Gamma Correction v6.01.a

  • Initial release in ISE 14.3 and Vivado 2012.3 design tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 Series

New Features

  • Fixed clock domain issues with registers in the AXI4-Lite connection

Resolved Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Resolved Issues (Vivado)

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (ISE)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

Known Issues (Vivado)

(Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

LogiCORE IP Gamma Correction v6.00.a

  • Initial release in ISE 14.2 and Vivado 2012.2 tools

Supported Devices (ISE)

  • All 7 series
  • All Virtex-6
  • All Spartan-6

Supported Devices (Vivado)

  • All 7 series

New Features

  • Separate clock domains between AXI4-Lite and AXI4-Stream

Bug Fixes

  • N/A

Known Issues (ISE)

(Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

Known Issues (Vivado)

(Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
(Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

LogiCORE IP Gamma Correction

v5.00.a

  • Initial release in ISE 14.1, Vivado 2012.1 tools

Supported Devices (ISE)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Virtex-6
  • Spartan-6

Supported Devices (Vivado)

  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000

New Features

  • 2012.1 tool support
  • Virtex-7, Kintex-7, Artix-7 and Zynq device support
  • AXI4-Stream interface support for the input and output interfaces
  • AXI4-Lite bus interface support for the processor interface
  • Support for YUV 4:2:2, YUV 4:2:0, and Mono video formats

Bug Fixes

  • N/A

Known Issues

  • N/A

LogiCORE IP Gamma Correction

v4.0

  • Initial release in ISE Design Suite 13.3

Supported Devices

  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX

New Features

  • ISE 13.3 design tools support
  • Virtex-7 and Kintex-7 device support
  • AXI4-Lite bus interface support for the EDK Pcore interface

Bug Fixes

(Xilinx Answer 33477)Why does the interpolation not work when I use the 12-bit input data?
(Xilinx Answer 38759)Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
(Xilinx Answer 38775)Why do I always get a single buffered constant interface, even when double buffered is selected?
(Xilinx Answer 38826)Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

Known Issues

(Xilinx Answer 38759)Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?

LogiCORE IP Gamma Correction v3.0

  • Initial release in ISE Design Suite 12.3

New Features

  • ISE 12.3 design tools support
  • Windows 64-bit support
  • New API
  • Improved speed when interpolation is used
  • Reduced footprint for Double-buffered interfaces

Bug Fixes

  • N/A

Known Issues

(Xilinx Answer 33477)Why does the interpolation not work when I use the 12-bit input data?
(Xilinx Answer 38759)Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
(Xilinx Answer 38775)Why do I always get a single buffered constant interface, even when double buffered is selected?
(Xilinx Answer 38826)Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

LogiCORE IP Gamma Correction v2.0

  • Initial release in ISE Design Suite 12.2

New Features

  • ISE 12.2 design tools support
  • Spartan-6 and Virtex-6 device support
  • Linux 32 and 64-bit support
  • XSVI bus interface support for the EDK Pcore interface

Bug Fixes

(Xilinx Answer 35130)Why do I get the following error when generating with a Design Linking License? ERROR:sim Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core.

Known Issues

(Xilinx Answer 33872)"ERROR:sim An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 33477)Why does the interpolation not work when I use the 12-bit input data?
(Xilinx Answer 38759)Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
(Xilinx Answer 37987)Where can I find UG762: Xilinx Streaming Video Interface User Guide?
(Xilinx Answer 38826)Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

LogiCORE IP Gamma Correction v1.0

  • Initial release in ISE Design Suite 11.1

New Features

  • Programmable Gamma tables
  • Single or three-color channel LUT structure
  • Optional interpolated output values
  • Selectable processor interface
    • EDK pCore - double buffered
    • EDK pCore - single buffered
    • General Processor
    • Constant
  • Configurable 8, 10, and 12-bit input and output
  • Delay match support for up to 3 sync signals
  • ISE 11.1 design tools support

Bug Fixes

  • N/A

Known Issues

(Xilinx Answer 32340)Why does my Image Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant?
(Xilinx Answer 33477)Why does the interpolation not work when I use the 12-bit input data?
(Xilinx Answer 33581)Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator?
(Xilinx Answer 33872)"ERROR:sim An IP generation script exited abnormally. Error found during generation."
(Xilinx Answer 35130)Why do I get the following error when generating with a Design Linking License? ERROR:sim Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core.
(Xilinx Answer 38759)Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
(Xilinx Answer 38826)Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
33477 LogiCORE Gamma Correction v2.0 - The interpolation does not work when I use the 12-bit input data N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
51483 ISE 14.2 / Vivado 2012.2 Video IP - Why does my Video IP lock up when a partial input frame is passed by the Video In To AXI-4 Stream input core? N/A N/A
51589 14.2 / 2012.2 Video IP - Why does the Video IP stop working (producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? N/A N/A
52215 14.3 / 2012.2 Video IP - Why does my core fail timing with a critical warning? N/A N/A
57773 Vivado 2013.2 Multimedia Video and Imaging - Why does the TREADY stall when using the TEST_PATTERN or BYPASS options available in some of the Video IP when the Include Debug Features option is enabled at generation? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38826 LogiCORE IP Gamma Correction v3.0 - Why are the two Least Significant Bits (LSB) incorrect when I select Interpolate? N/A N/A
37987 Where can I find UG762, Xilinx Streaming Video Interface User Guide? N/A N/A
35130 LogiCORE IP Image Processing Pipeline Cores - The following error is received when generating with a Design Linking License: "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core" N/A N/A
33872 LogiCORE IP Image Processing Pipeline Cores - "ERROR:sim - An IP generation script exited abnormally. Error found during generation." or "ERROR:Sim - assertMcrCacheRoot : Temp environment variable set is too long ..." N/A N/A
33581 LogiCORE Image Processing Pipeline v1.0 - Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator? N/A N/A
33477 LogiCORE Gamma Correction v2.0 - The interpolation does not work when I use the 12-bit input data N/A N/A
32340 11.1 CORE Generator - Why do my Image Processing Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant? N/A N/A
32136 LogiCORE IP Image Processing Pipeline - Release Notes and Known Issues N/A N/A
AR# 32135
Date 07/17/2018
Status Archive
Type Release Notes
IP
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