Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Gamma Correction Core.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

Solution

• (Xilinx Answer 34828) - How do I simulate my Video IP pCore in EDK?

• Initial release in ISE 14.3 and Vivado 2012.3 design tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• Fixed clock domain issues with registers in the AXI4-Lite connection

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• Initial release in ISE 14.2 and Vivado 2012.2 tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• Separate clock domains between AXI4-Lite and AXI4-Stream

• N/A

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• Initial release in ISE 14.1, Vivado 2012.1 tools

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
• Virtex-6
• Spartan-6

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000

• 2012.1 tool support
• Virtex-7, Kintex-7, Artix-7 and Zynq device support
• AXI4-Stream interface support for the input and output interfaces
• AXI4-Lite bus interface support for the processor interface
• Support for YUV 4:2:2, YUV 4:2:0, and Mono video formats

• N/A

• N/A

• Initial release in ISE Design Suite 13.3

• Virtex-7
• Virtex-7 XT (7vx485t)
• Virtex-7 -2L
• Kintex-7
• Kintex-7 -2
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX

• ISE 13.3 design tools support
• Virtex-7 and Kintex-7 device support
• AXI4-Lite bus interface support for the EDK Pcore interface

• (Xilinx Answer 33477) - Why does the interpolation not work when I use the 12-bit input data?
• (Xilinx Answer 38759) - Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
• (Xilinx Answer 38775) - Why do I always get a single buffered constant interface, even when double buffered is selected?
• (Xilinx Answer 38826) - Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

• (Xilinx Answer 38759) - Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?

• Initial release in ISE Design Suite 12.3

• ISE 12.3 design tools support
• Windows 64-bit support
• New API
• Improved speed when interpolation is used
• Reduced footprint for Double-buffered interfaces

• N/A

• (Xilinx Answer 33477) - Why does the interpolation not work when I use the 12-bit input data?
• (Xilinx Answer 38759)- Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
• (Xilinx Answer 38775)- Why do I always get a single buffered constant interface, even when double buffered is selected?
• (Xilinx Answer 38826)- Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

• Initial release in ISE Design Suite 12.2

• ISE 12.2 design tools support
• Spartan-6 and Virtex-6 device support
• Linux 32 and 64-bit support
• XSVI bus interface support for the EDK Pcore interface

• (Xilinx Answer 35130) - Why do I get the following error when generating with a Design Linking License? ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.

• (Xilinx Answer 33872) - "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 33477) - Why does the interpolation not work when I use the 12-bit input data?
• (Xilinx Answer 38759)- Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
• (Xilinx Answer 37987) - Where can I find UG762: Xilinx Streaming Video Interface User Guide?
• (Xilinx Answer 38826)- Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

• Initial release in ISE Design Suite 11.1

• Programmable Gamma tables
• Single or three-color channel LUT structure
• Optional interpolated output values
• Selectable processor interface
  • EDK pCore - double buffered
  • EDK pCore - single buffered
  • General Processor
  • Constant
• Configurable 8, 10, and 12-bit input and output
• Delay match support for up to 3 sync signals
• ISE 11.1 design tools support

• N/A

• (Xilinx Answer 32340) - Why does my Image Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant?
• (Xilinx Answer 33477) - Why does the interpolation not work when I use the 12-bit input data?
• (Xilinx Answer 33581) - Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator?
• (Xilinx Answer 33872) - "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 35130) - Why do I get the following error when generating with a Design Linking License? ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core.
• (Xilinx Answer 38759)- Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design?
• (Xilinx Answer 38826)- Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate?

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