This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Gamma Correction Core.
The following information is listed for each version of the core:
LogiCORE IP Gamma Correction core IP Page:
https://www.xilinx.com/products/intellectual-property/ef-di-gamma.html
Note: The LogiCORE IP Gamma Correction is in maintenance mode and not recommended for new designs.
General LogiCORE IP Gamma Correction Issues
LogiCORE IP Gamma Correction v6.01.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Resolved Issues (ISE)
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Resolved Issues (Vivado)
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Known Issues (ISE)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
Known Issues (Vivado)
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
LogiCORE IP Gamma Correction v6.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues (ISE)
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Known Issues (Vivado)
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
LogiCORE IP Gamma Correction
v5.00.aSupported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues
LogiCORE IP Gamma Correction
v4.0Supported Devices
New Features
Bug Fixes
| (Xilinx Answer 33477) | Why does the interpolation not work when I use the 12-bit input data? |
| (Xilinx Answer 38759) | Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design? |
| (Xilinx Answer 38775) | Why do I always get a single buffered constant interface, even when double buffered is selected? |
| (Xilinx Answer 38826) | Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate? |
Known Issues
| (Xilinx Answer 38759) | Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design? |
LogiCORE IP Gamma Correction v3.0
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 33477) | Why does the interpolation not work when I use the 12-bit input data? |
| (Xilinx Answer 38759) | Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design? |
| (Xilinx Answer 38775) | Why do I always get a single buffered constant interface, even when double buffered is selected? |
| (Xilinx Answer 38826) | Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate? |
LogiCORE IP Gamma Correction v2.0
New Features
Bug Fixes
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR:sim Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
Known Issues
| (Xilinx Answer 33872) | "ERROR:sim An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 33477) | Why does the interpolation not work when I use the 12-bit input data? |
| (Xilinx Answer 38759) | Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design? |
| (Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
| (Xilinx Answer 38826) | Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate? |
LogiCORE IP Gamma Correction v1.0
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 32340) | Why does my Image Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant? |
| (Xilinx Answer 33477) | Why does the interpolation not work when I use the 12-bit input data? |
| (Xilinx Answer 33581) | Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator? |
| (Xilinx Answer 33872) | "ERROR:sim An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR:sim Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
| (Xilinx Answer 38759) | Why are simulation and hardware results wrong, when I have multiple Gamma cores in my design? |
| (Xilinx Answer 38826) | Why are the 2 Least Significant Bits (LSB) incorrect, when I select Interpolate? |
| AR# 32135 | |
|---|---|
| Date | 07/17/2018 |
| Status | Archive |
| Type | Release Notes |
| IP | |