UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32165

Virtex-5 - GTX transceiver test using IBERT

Description

When testing GTX with IBERT

- the PLL does not lock

- the PLL locks unstable

- the PLL locks only if the DC coupling condition is chosen

- too much jitter is present in transmitted signal

- errors are revealed at receiver side

Solution

IBERT allows a fast and easy-to-use method for testing Virtex-4 and Virtex-5 transceivers. In the 10.1 Virtex-5 GTX IBERT version, the embedded 100 Ohm terminating resistor of the GTX reference clock is disabled by default. This results in a high impedance input characteristic that is only intended for factory testing or with external differential termination.

The reference clock termination is essential for correct GTX characterization. The absence of it sometimes prevents the PLL from locking so that the transceiver will not work at all. What is more dangerous, if the PLL succeeds in locking, both transmitter and receiver performances are compromised.

The internal termination can be easily turned on asserting CLKRCV_TRST = 1 directly in IBERT. In the 11.1 IBERT release the default value will be turned in 1.

AR# 32165
Date Created 02/23/2009
Last Updated 12/15/2012
Status Active
Type General Article