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AR# 32188

Serial RapidIO - Virtex-5 FXT core might show data errors and "input-error stopped" state

Description

Known Issue: v5.3, v5.2, v5.1 Rev1, v5.1, v4.3

The Serial RapidIO Core is affected by the problem outlined in (Xilinx Answer 32164). The issue might appear in the SRIO Core as protocol errors or the core entering the "input-error stopped" state.

Solution

To work around this issue, the clock correction length can be set to 2 instead of 1 as the SRIO Core currently uses. The following attributes should be changed in the RocketIO wrapper:

CLK_COR_DET_LEN = 2

CLK_COR_ADJ_LEN = 2

CLK_COR_MIN_LAT = 21

CLK_COR_MAX_LAT = 24

CLK_COR_SEQ_1_1 = "0111111101"

CLK_COR_SEQ_1_2 = "0111111101"

CLK_COR_SEQ_1_ENABLE = "0011"

These attribute settings will be verified in hardware prior to the SRIO v5.4 core release. This Answer Record will be updated as validation progresses.

Revision History

03/17/2009 - Initial Release

06/30/2009 - Updated fix schedule, pushed to v5.4

AR# 32188
Date Created 03/17/2009
Last Updated 12/15/2012
Status Active
Type General Article