keywords: DCM_ADV, Period Constraint, Virtex 4, 10.1
I'm using a DCM in High Frequency Mode with only the DLL outputs. The Virtex-4 data sheet states that a DCM for a -12 speed grade part can have an input clock of 500 MHz. When I place a timing constraint between 477 MHz and 500 MHz on the input clock, I get the following Warning during a static analysis:
WARNING:Timing:3329 - Timing Constraint "%s" fails the pulse width check for DCM_ADV block "DCM_inst_name" because the low pulse width value (1000 ps) is less than the minimum internal pulse width of 1050 for frequencies between 450 MHz and 500 MHz. Please increase the period of the constraint to remove this timing failure.
Why do I get this warning when the data sheet states that the DCM can run at up to 500 MHz?
This warning should not be issued.
It is safe to ignore if you verify the following:
- The part you are targeting is a Virtex 4 with a -12 speed grade
- You are only using the DLL portion of the DCM
This warning is scheduled to be removed in 11.1.