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AR# 32195

Serial RapidIO v5.2, v5.3 - Virtex-4 FX 3.125G, 4x core might not meet timing

Description

A Serial RapidIO v5.2, v5.3 or v5.4 Core generated for the Virtex-4 FX FPGA, with x4 lanes and 3.125G line rate might fail to meet timing on the following constraints:

TS_CLK0_BUF = PERIOD TIMEGRP "CLK0_BUF".4 ns HIGH 50% INPUT_JITTER 0.1 ns PRIORITY 0
TS_UCLK = PERIOD TIMEGRP "UCLK" 6.4 ns HIGH 50% INPUT_JITTER 0.1 ns PRIORITY 0

Solution

There were some modifications to the SRIO v5.5 Core (released with ISE Design Suite 12.1) that should relieve the timing difficulties for most cases. In some rare instances, however, this timing constraint may still fail which may require advanced timing closure techniques in order to meet timing. In particular, Area Groups that are large enough to constrain the Core to a particular area have helped improve timing, as well as using different cost tables (-t option in Map/Par) and/or SmartXplorer.


Revision History
04/27/2009 - Initial Release
06/30/2009 - Updated fix schedule
04/08/2010 - Updated fixed version

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 32195
Date Created 04/29/2009
Last Updated 09/25/2012
Status Archive
Type Known Issues