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AR# 32196

Serial RapidIO v5.2 - Release Notes and Known Issues for ISE 11.1


This Release Notes and Known Issues Answer Record is for the Serial RapidIO v5.2 Core, which was released in ISE 11.1 and contains the following information:

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues and design tools requirements, see the IP Release Notes Guide at:



New Features

- ISE 11.1 Tool Support

Resolved Issues

(Xilinx Answer 32189) Latches inferred in VHDL example design

- Version fixed: v5.2

- CR#509670 - Added intermediate values for partial register and combinational assignments.

Known Issues in v5.2

- (Xilinx Answer 32614) PHY does not pass CRF bit correctly on RX frames

- Version to be fixed: v5.4

- CR# 519603

- (Xilinx Answer 32195) Virtex-4 FXT 3.125G, 4x core might not meet timing

- Version to be fixed: v5.4

- CR# 506364

- (Xilinx Answer 32188) Virtex-5 FXT core might show data errors and "input-error stopped" state

- Version to be fixed: v5.4

- CR# 510781 - Virtex-5 GTX clock compensation logic might corrupt post 8b/10b data.

- (Xilinx Answer 32122) Re-Transmit Suppression Support bit set incorrectly as 1'b0

- Version to be fixed: v6.0

- CR# 507334

- (Xilinx Answer 32063) Buffer layer might corrupt single-cycle RX packets

- Version to be fixed: v6.0

- CR# 498073

- (Xilinx Answer 32316) If 16-bit Device IDs are used, treq_vld_n can assert before treq_sof_n on an SWRITE

- Version to be fixed: Fix Not Scheduled

- CR# 514611

- (Xilinx Answer 30023) Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT core configurations are unable to train down to x1 mode in Lane 2. Traindown in Lane 0 works successfully, but the Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT configurations are unable to Traindown in Lane 2. The RocketIO transceivers only allow Traindown to the channel bonding master.

- Version to be fixed: Fix Not Scheduled

- CR# 457109.

- (Xilinx Answer 30021) Core reinitialization during error recovery causes recoverable protocol error. This is a corner condition that could occur if the core is forced to reinitialize (i.e., - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable.

- Version to be fixed: Fix Not Scheduled

- CR# 457885

- (Xilinx Answer 29522) Post-Synplicity synthesis implementation runs might exhibit UCF failures. Synplicity generated net names are not consistent with XST generated names and might not be consistent between core types. The ".ucf" file must be edited in these failure cases.

- Version to be fixed: Fix Not Scheduled

- CR# 447782

- (Xilinx Answer 24982) PNA cause field might occasionally reflect a reserved value. The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols.

- Version to be fixed: Fix Not Scheduled

- CR# 436767

(Xilinx Answer 24970) Control Symbols might be lost on reinit. This is an unusual and ultimately recoverable error. Set the Additional Link Request Before Fatal value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state.

- Version to be fixed: Fix Not Scheduled

- CR# 436768

(Xilinx Answer 24968) Logical Rx does not support core side stalls. The Rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.

- Version to be fixed: Fix Not Scheduled

- CR# 436770

Revision History

04/27/2009 - Initial Release

04/29/2009 - Added AR 32614 to Known Issues

06/30/2009 - Updated fix schedule for ARs 32614, 32195, 32188

AR# 32196
Date 12/15/2012
Status Active
Type General Article
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