This Release Note and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v5.2 Core, released in ISE software 11.1, and contains the following information:
- New Features
- Bug Fixes
- General Information
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
New Features in v5.2
- ISE 11.1 software support
- Support removed for the Spartan(R)-3A DSP device family
- Tested with Virtex-5 TXT FPGA
Bug Fixes in v5.2
- Increased MAP and PAR effort levels to high in the implementation script
- Moved TX_CLK pin LOC to a GCLK pin for Spartan-3AN devices
- Version fixed: v5.2
- CR 503557
- Modified DCM phase shifts for select families in the sample ucf file to achieve timing closure in 11.1
- Added vsim vopt argument to ModelSim simulation scripts to prevent the tool from optimizing out unused signals that are displayed in the waveform viewer
- Version fixed: v5.2
- CR 480217
- The Tx and Rx cores are provided with default timing constraints in the UCF file generated with the core. Depending on the core configuration, target architecture, and speed grade, the core might run significantly faster. The user can modify the constraints to meet their performance requirements. As long as all timing constraints are met, the SPI-3 Link Core will operate at the user specified rate. Note that the best way to verify timing closure is with user logic, rather than the example design. Implementing only the example design might artificially limit the performance of the SPI-3 Link Core (e.g., if the User Interface is routed to I/O pins).
- A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement for Spartan-3/3E parts. This solution is necessary only if the system's timing budget cannot permit the Link Core to exceed the 2 ns input requirement.
Known Issues in v5.2
- If the core does not meet timing with high effort for MAP and PAR, users can try running PAR with the "-xe n " option.
(Xilinx Answer 34527) Some designs may fail timing
- CR 510018
-When using the example implementation script and ucf file for Spartan-3AN devices, PAR will report timing violations with the following message: "WARNING:Par:62 - Your design did not meet timing." Timing closure can be achieved by modifying the DCM PHASE_SHIFT values in the UCF file.
04/27/2009 - Initial Release