AR# 32202


Block Memory Generator v3.1 - Release Notes and Known Issues for ISE 11.1


Keywords: CORE, Generator, mem, memory, asynch, asymmetric, nonsymmetric, non-symmetric, block RAM, RAMB, block RAM, BRAM, RAMB16, RAMB, simulation, UniSim, SimPrim, unisims, simprims, NetGen, SDF

This Release Notes and Known Issues Answer Record is for the Block Memory Generator v3.1 Core, released in ISE 11.1, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


General Information
The Xilinx Block Memory Generator v3.1 LogiCORE should be used in all new Virtex-5, Virtex-4 and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.

Please see the Block Memory Core Migration Kit available at:

Also, see (Xilinx Answer 24848) for known issues of the migration kit, and (Xilinx Answer 29168) for changes made from pre-v2.4 XCO parameters.

A new CORE Generator feature is available to upgrade the Block Memory Generator from v2.4 to the latest core. This feature is part of CORE Generator, and it is visible only if you open an existing CORE Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the CORE Generator User Guide (Software Manuals).

(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator
(Xilinx Answer 31378) BitGen DRC Warnings Are Produced When DOA is Unused and DIA is Tied to Ground
(Xilinx Answer 31377) "ERROR:ip - build_algo_return: For the configured RAM size, the number of block RAMs used exceeds the maximum number of block RAMs in all available architectures (550)?

New Features in v3.1

- Display of BRAM utilization in terms of 9K, 18K and 36K primitives
- Support for Low Power algorithm (Virtex-5, Virtex-4, and Spartan-3/3E/3A/3AN/3ADSP)
- Disabled option to keep a port Always Enabled while using the Low Power algorithm

Resolved Issues in v3.1

- Estimated BlockRAM Usage is incorrect
- Version fixed : 3.1
- CR# 491178, 481514
- In previous versions of the core, the BRAM utilization was always reported in terms of 18K primitives, as a result of which the actual BRAM utilization was different from the number reported when 36K primitives were used. The GUI will now report BRAM utilization separately in terms of 9K, 18K and 36K blocks.

(Xilinx Answer 32290) READ_FIRST mode does not work as expected in Virtex-5 Single Primitive ECC configurations
- Version fixed : 3.1
- CR# 498772

(Xilinx Answer 32037) Discrepancy in latency reported in GUI for ECC configurations
- Version fixed : 3.1
- CR# 501642, 493653

- Migration from Behaviorial model to structural model does not flow smoothly
- Version fixed : 3.1
- CR# 475649

Known Issues in v3.1

- Power estimation figures in the data sheet are preliminary.

(Xilinx Answer 31377) CoreGen GUI Console displays error "For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the chosen architecture"

(Xilinx Answer 24034) Core does not generate for large memories
-The maximum size of the memory that can be generated varies depending on the machine the CORE Generator is run on. For example, a Dual Pentium-4 server running at 3.6GHz with two Gig RAM can generate a memory core that is 1.8 MBits or 230 K Bytes.
- CR 415768

(Xilinx Answer 23744) Out-of-range address input can cause the core to generate Xs on the DOUT bus

Device Issues
The Virtex-4 and Virtex-5 Errata is located at:
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.

Revision History
04/27/2009 - Initial Release
AR# 32202
Date 04/21/2009
Status Active
Type General Article
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