General Description: FPGA Express versions 2.x and 3.0 implement large comparators using general combinatorial logic only by default, instead of using carry logic optimized for Xilinx devices along with the required combinatorial logic.
Straight combinatorial logic may take up less space (fewer LookUp Tables), but will run slower and have less predictable timing than an implementation using carry logic.
This issue has been resolved with version 3.1 of FPGA Express.
Solution
To force FPGA Express infers carry logic, use the following syntax when describing compare functionality.
Verilog:
(A-B) >> 0; instead of A >> B;
VHDL:
(A-B) > 0; instead of A > B;
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AR# 3224
Date
08/28/2001
Status
Archive
Type
General Article
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