Do Xilinx CPLDs have maximum rise/fall time specifications?
The recommended maximum rise/fall time for a signal that is routed to combinatorial logic is 50 nS.
For signals that use global routing resources (Global Clock, Global Output Enable, and Global Set/Reset), Xilinx recommends that the maximum rise/fall time not exceed 10 nS.
Signals that go to registered elements are not specified, but should also meet the 50 nS requirement. This is because a signal to a register must meet the setup time requirement, so it is assumed it is stable by the time the clock signal arrives.
These values may be exceeded, provided that the input signal is monotonic.
Rise (Tr) and fall (Tf) times are specified in the individual CoolRunner XPLA3 Data Sheets.
The recommended maximum rise/fall times for any input is 20 nS. If these values are exceeded, Xilinx recommends that you enable Schmitt Trigger circuitry for that input. To enable Schmitt Trigger circuitry, enter the following line in your User Constraints File (UCF) :
net netname schmitt_trigger;