When I attempt to lock my pins using the following constraint:
INST Base_0/*S4 LOC=SLICE_X3Y119;
INST Base_0/*S4 BEL= D6LUT;
INST Base_0/*S4 LOCK_PINS=I0:A1,I1:A2,I2:A3,I3:A4,I4:A5,I5:A6;
I receive an error similar to the following:
"ERROR:Pack:1676 - Error parsing LOCK_PINS constraint I0:A1, I1:A2, I2:A3, I3:A4,I4:A5, I5:A6. Logical input I1 is not a valid logical input."
How can I prevent this error?
To work around this error, lock down the placement of the LUT pins using the "ALL" keyword.
Example:
INST Base_0/*S4 LOC=SLICE_X3Y119;
INST Base_0/*S4 BEL= D6LUT;
INST Base_0/*S4 LOCK_PINS=ALL;
AR# 32285 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |