You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
F1.4, FPGA Express 2.0: Inverting Pin on HDL instantiation does not work
Keywords: FPGA Express, 1.2, 2.0, instantiate, invert, <>
When instantiating a cell within HDL (VHDL or Verilog) to be compiled by
FPGA Express, if a user inverts the signal in the port map, the pin is renamed
in bus style. For example
STARTUP U1 (.GSR(!reset));
would give a pin named GSR<0>. This will cause connectivity problems with the
The workaround is to have an intermediate signal to invert the reset signal
before the pin assignment. Example:
foo = !reset;
STARTUP U1 (.GSR(foo));
Was this Answer Record helpful?