AR# 32360


11.1 ISE Simulator (ISim) - Issues when using assert / report commands in VHDL


I use the Assert / Report VHDL I/O functions in order to write messages to the simulator console. However, when I write messages using this syntax:

assert false report Message.all severity warning;


the output shows up incomplete when running the simulation in batch mode.

For example:

Finished circuit initialization process.

(/testbench/config_test/).the design...

Running the same simulation via the ISim GUI results in the correct console output:

Finished circuit initialization process.

at 200 ns: Note: Resetting the design...


How can I resolve this issue?


This is a known issue with ISim in ISE Design Suite 11.1 tools and it has been fixed in ISE Design Suite 11 Update 2 (11.2) . Please download and install the latest ISE Design Suite update from the Download Center at:

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33381 ISE Design Suite 11 - ISE Simulator (ISim) Known Issues N/A N/A
AR# 32360
Date 12/15/2012
Status Active
Type General Article
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