We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32415

EDK 11.1, plbv46_pcie_v3_00_a - Data sheet contains incorrect information


The plbv46_pcie_v3_00_a Product Specification document contains the following discrepancies: 

- x1, x4, and x8 lane support; this should be corrected to x1 lane support only. 

- LinkUp output needs to be added to the I/O port list. 

- Footnotes in resources table need to have 6-ipifbar, 3 pciebar, and x8 lane support changed to: 1-ipifbar, 1-pcibar, and x1 lane support.


These discrepancies have been fixed in the plbv46_pcie_v3_00_b Product Specification, and is available in EDK 11.1. 

EDK 11.1 is available at:  

AR# 32415
Date 05/23/2014
Status Archive
Type General Article
  • EDK - 11.1
Page Bookmarked