When reading the timing report, I noticed that the Clock Uncertainty associated with the PLL/DCM is pessimistic, which is caused by the Discrete Jitter also being pessimistic. Why?
The Discrete Jitter portion of the Clock Uncertainty equation for PLL and DCM components is very conservative. The actual values from characterization are approximately 30% less than the reported values in the timing report.
This is scheduled to be fixed in the next quarterly update or major release of the speed files.