AR# 32441

11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic

Description

Keywords: discrete, jitter, pll, dcm, clock, uncertainty, pessimistic

When reading the timing report, I noticed that the Clock Uncertainty associated with the PLL/DCM is pessimistic, which is caused by the Discrete Jitter also being pessimistic. Why?

Solution

The Discrete Jitter portion of the Clock Uncertainty equation for PLL and DCM components is very conservative. The actual values from characterization are approximately 30% less than the reported values in the timing report.

This is scheduled to be fixed in the next quarterly update or major release of the speed files.

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AR# 32441
Date	04/22/2009
Status	Archive
Type	General Article

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AR# 32441

11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic

Description

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