2. Support
  3. AR# 3245: M1.4 Map - Mapper unable to merge a RAM and Flop with opposite clock polarities
  4. AR# 32456: 11.1 Timing Known Issue - MAXSKEW constraint shows a violation, but the report says it met timing

AR# 32456

11.1 Timing Known Issue - MAXSKEW constraint shows a violation, but the report says it met timing

Description

My MAXSKEW constraint shows a violation, but the report says it met timing.

Following is an example:

Timing constraint: NET "SDI_Ref_Clk1" MAXSKEW = 0.001 ns;

1 net analyzed, 1 failing net detected.

1 timing error detected.

Maximum net skew is 0.208ns.

--------------------------------------------------------------------------------

Slack: -0.207ns SDI_Ref_Clk1

Report: 0.208ns skew meets 0.001ns timing constraint by -0.207ns

From To Delay(ns) Skew(ns)

SLICE_X23Y59.X E7.O1 1.037 0.208

SLICE_X23Y59.X D7.O1 1.037 0.208

Solution

This is a known issue. Currently, the reports states:

Report: 0.208ns skew meets 0.001ns timing constraint by -0.207ns

Xilinx is working to change it so that it correctly acknowledges a failing path and states that the path "fails" by X ns.

AR# 32456
Date 12/15/2012
Status Active
Type General Article