UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 32482: 11.1 PlanAhead - Does PlanAhead DRC report single-ended clocks on the N side of a differential pair?

AR# 32482

11.1 PlanAhead - Does PlanAhead DRC report single-ended clocks on the N side of a differential pair?

Description

I accidentally constrained my single-ended clock to the N side of a Global Clock differential pair.  

 

Why did PlanAhead allow me constrain the clock to this location, and why did DRC not report it?

Solution

PlanAhead currently Auto-Places clocks only to the P side, but allows you to assign the clock to the N side without a DRC error.  

 

This problem is scheduled to be fixed in a future software release.

AR# 32482
Date 05/21/2014
Status Archive
Type General Article