We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32521

11.1 Virtex-5 MAP Known Issues - Incorrect optimization of latch with Gate driven by constant "1" but GE driven by active signal


I have a latch in my design with G constantly high and an active signal on D. It has been optimized away so as to pass through the D signal despite the fact that GE is active. Is this optimization problem a known issue?


This latch optimization issue is scheduled to be fixed in ISE 11.2.

AR# 32521
Date 05/23/2014
Status Archive
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
  • ISE Design Suite - 11.1
Page Bookmarked