AR# 32521


11.1 Virtex-5 MAP Known Issues - Incorrect optimization of latch with Gate driven by constant "1" but GE driven by active signal


I have a latch in my design with G constantly high and an active signal on D. It has been optimized away so as to pass through the D signal despite the fact that GE is active. Is this optimization problem a known issue?


This latch optimization issue is scheduled to be fixed in ISE 11.2.

AR# 32521
Date 05/23/2014
Status Archive
Type General Article
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