AR# 32524

11.1 Virtex-5 PACK Known Issues - Unroutable carry chain connections

Description

My design has an unrouted carry chain connection (COUT-->CIN slice pins) and when I examine the partially routed design (NCD) in FPGA Editor, I see that the slices are not aligned properly so that the dedicated carry chain routing resource is used. Why weren't the carry chain slices aligned properly? Shouldn't the router still be able to route the non-aligned carry connections?

Solution

There can be multiple reasons that carry chain slices are not aligned:

- The carry chain will be broken into multiple segments if it is too tall for the device or its area group range.

- The carry chain may have a split where a COUT pin drives multiple CIN pins.

- Design constraints may prevent the proper alignment of the carry chain.

When a carry chain is broken, it becomes necessary for the packer to reserve the AX pin for route-thru access to the CARRYINIT logic (see Logic Block Editor in FPGA Editor for connection details). If the MUXCY involved has an active signal on the DI pin, it is necessary to move that signal to a LUT pack-thru using the O5 pin of the LUT complex so that the AX pin is available for CARRYINIT. There is a known problem in 11.1 that this pack-thru optimization does not occur in some cases, leaving an unroutable configuration because the AX route-thru is not available. This problem will be fixed in ISE 11.2. Meanwhile, a work around is to instantiate a LUT1 buffer on the DI signal and use LUTNM constraints to pair it into the same LUT complex as the LUT driving the MUXCY S pin.

Was this Answer Record helpful?

AR# 32524
Date	09/09/2010
Status	Active
Type	General Article
Tools	ISE Design Suite - 11.1

Page Bookmarked

AR# 32524

11.1 Virtex-5 PACK Known Issues - Unroutable carry chain connections

Description

Solution

Applications

Products

Developer Zone

Support

About Xilinx