AR# 32528: 11.1 Spartan-3A Place Known Issues - Timing driven mapping fails with ERROR:Place:848
AR# 32528
11.1 Spartan-3A Place Known Issues - Timing driven mapping fails with ERROR:Place:848
Description
Keywords: Place, -timing, ERROR:Place:848
My design places ok in PAR when I use non-timing driven mapping, but when I run with timing driven mapping I get the following placement error. Why would timing driven mapping fail when the design is clearly feasible?
ERROR:Place:848 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further information see the "Quadrant Clock Routing" section in the Spartan3a dsp Family Datasheet.
Solution
When timing driven mapping is run, some additional constraining occurs to control the placement of "local clocks". Local clocks are clock nets that are driven by input I/O configurations without the use of dedicated clock buffers. If there are a large number of local clocks in a design, the additional constraints that are applied by the clock placer may cause the design to fail during the clock placement phase.
This problem will be fixed in ISE 11.2 so that if clock placement fails, placement will be reattempted without local clock constraints. Meanwhile, if clock placement fails, it is possible to manually disable local clock placement by setting the following environment variable:
Windows SET XIL_PAR_NOIORGLLOCCLKSPL=1
Linux setenv XIL_PAR_NOIORGLLOCCLKSPL 1
For general information about setting ISE environment variables, see (Xilinx Answer 11630).