UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32545

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.6 - Implementation of GMII interface fails in MAP due to Place error

Description

Implementation of Tri-speed GMII interface fails in MAP due to not being able to place a clock pin and BUFG in the same half of the device. When a design with EMAC0 and EMAC1 configured with Tri-speed GMII interface is implemented, it fails in MAP with the following error:

"ERROR:Place:592 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair."

Solution

To avoid this error, add the following constraint in the UCF:

INST "mii_tx_clk_0" LOC = "BANK3";

AR# 32545
Date Created 04/21/2009
Last Updated 12/15/2012
Status Active
Type General Article