AR# 32550


Block Memory Generator v3.1 - Simulation issues with asynchronous reset


When using the Spartan-6 asynchronous reset feature of the Block Memory Generator core (RST_TYPE = "ASYNC"), the user may get unexpected output from structural or behavioral models. A few examples of unexpected behavior are: 

1. Reset occurs asynchronously if Reset goes high and Enable goes low at the same time, even though the Reset Priority is set to "CE", and reset should not happen unless both RST and EN are high. 

2. Unknown data continues to remain at the output when the address changes from an invalid address to a valid address at the same time when RST goes high.


These issues appear to be simulator delta issues, and have been observed with both ModelSim and NCSIM. These are not core issues. 


In order to avoid these issues, it is recommended that the user should not change all input stimuli at the same time when using the asynchronous reset feature. In other words, RST, EN / REGCE, ADDR, CLK should not change at the same time.\ 


This AR may no longer be necessary--see AR 32815

AR# 32550
Date 10/11/2014
Status Partner Exclusive
Type General Article
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