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MIG 3.1, Virtex-5 FPGA DDR2 - TWTR violations might occur at low frequencies in simulation and hardware
The DDR2 specification requires TWTR to be a minimum of 2*TCK.
TWTR is the time from the last DQ toggling during the write to the read command.
In the Virtex-5 FPGA DDR2 MIG design, it is possible for this TWTR specification to be violated when operating at lower frequencies.
Violations can occur in simulation and hardware.
The Virtex-5 FPGA DDR2 ddr2_ctrl.v/.vhd calculates the number of TWTR clock cycles based on the clock frequency and TWTR specification of the memory as follows (example in Verilog):
localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD;
When the frequency is low, it is possible for the design to equate TWTR_TMP_MIN to be less then 2.
This violates the TWTR minimum timing of 2*TCK.
For example, if TWTR = 7500 and the CLK_PERIOD = 8000 (125MHz), TWTR_TMP_MIN is assigned '1'.
To work around this issue, add a check to the assignment of TWTR_TMP_MIN to ensure the value is always 2 or greater.
This issue exists in MIG 3.1 and all previous releases.
It is resolved in MIG 3.2.
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