Description

Solution

The Virtex-5 FPGA DDR2 ddr2_ctrl.v/.vhd calculates the number of TWTR clock cycles based on the clock frequency and TWTR specification of the memory as follows (example in Verilog): 

localparam integer TWTR_TMP_MIN = (TWTR + CLK_PERIOD)/CLK_PERIOD; 

When the frequency is low, it is possible for the design to equate TWTR_TMP_MIN to be less then 2.

This violates the TWTR minimum timing of 2*TCK. 

For example, if TWTR = 7500 and the CLK_PERIOD = 8000 (125MHz), TWTR_TMP_MIN is assigned '1'.  

To work around this issue, add a check to the assignment of TWTR_TMP_MIN to ensure the value is always 2 or greater. 

This issue exists in MIG 3.1 and all previous releases.

It is resolved in MIG 3.2.