UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 32628: SPI-4.2 v9.1 - "ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region..."

AR# 32628

SPI-4.2 v9.1 - "ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region..."

Description

Keywords: CORE Generator, PL4, packet, SONET, oif, open, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa, spi4.2, spi4-2, Virtex-5

For some Sink core configurations (Global Clocking with IDELAY inserted on RDClk), the following errors might occur in Map:

"ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region CLOCKREGION_X1Y3. The IODELAY block core_pl4_snk_top0/U0/io0/dpa2/dpa_top0/DATAPAIR12/SLAVE_DELAY has an IDELAY_TYPE attribute of either FIXED or VARIABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region"

Solution

This is a known issue with Map and the IODELAY_GROUP contraint.

To work around this problem, do the following:

1. Comment out the following constraints in the UCF file:

## INST "sict1" IODELAY_GROUP = sink_idelay ;
## INST "<sink_core_instant_name>/U0/io0/dpa2/dpa_top0/DATAPAIR*/MASTER_DELAY" IODELAY_GROUP = sink_idelay ;
## INST "<sink_core_instant_name>/U0/io0/dpa2/dpa_top0/DATAPAIR*/SLAVE_DELAY" IODELAY_GROUP = sink_idelay ;
## INST "<sink_core_instant_name>/U0/io0/dpa2/dpa_top0/CTLPAIR*/SLAVE_DELAY" IODELAY_GROUP = sink_idelay ;
## INST "<sink_core_instant_name>/U0/io0/dpa2/dpa_top0/CTLPAIR*/MASTER_DELAY" IODELAY_GROUP = sink_idelay ;

2. Add the LOC constraint for the IDELAYCTRL to place it in the same bank as RDat, RCtl, and RDClk.

For example:
INST "RCtl*" LOC = "Bank12";
INST "RDat*" LOC = "Bank12";
INST "RDClk*" LOC = "Bank12";
INST "sict1" LOC = IDELAYCTRL_X2Y3 ; ## IDELAYCTRL LOC constraint

You can follow the same IDELAYCTRL instantiation and placement that is detailed in "Instantiating IDELAYCTRL for Virtex-4" section, on page 167 of the SPI-4.2 Core v9.2 User Guide.


Revision History
05/04/2009 - Initial Release
06/10/2009 - Updated with work-around information
AR# 32628
Date 06/22/2009
Status Active
Type General Article
Page Bookmarked