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  3. AR# 3263: M1.x EPIC: How do I select an entire net?
  4. AR# 32631: 11.1 Timing - Why is my PLL Jitter lower than my System Jitter?

AR# 32631

11.1 Timing - Why is my PLL Jitter lower than my System Jitter?

Description

When I look at my timing report, the DCM Jitter calculations correctly use my System Jitter. However, when I look at my PLLs, the PLL Jitter is less than the System Jitter.

Is this possible, or is there a problem with my timing report?

Solution

By design, the PLLs can reduce jitter. This reduction in jitter is reflected in timing reports. Therefore, it is possible to see PLL Jitter at values lower than System Jitter.

AR# 32631
Date 12/15/2012
Status Active
Type General Article