Product Change Notice Starting with this release, further development of the AccelDSP synthesis tool has been discontinued. You may continue to use this version of the tool with ISE Design Suite 11. The tool will not be included in ISE Design Suite 12.
Frequently Asked Questions - How do I switch between MATLAB versions used with AccelDSP? See (Xilinx Answer 22966). - Is there a way to terminate or kill a process once I have launched the next step in my design flow? See (Xilinx Answer 31602). - AccelDSP appears to hang when I launch it, or it takes a long time to initialize. See (Xilinx Answer 31293).
General Issues - When running the Generate RTL step, error messages occur (because of certain coding styles): "E-ERR-0009): Failed to generate RTL model from fixed-point design for unknown reasons!" or "Out of memory." See (Xilinx Answer 31098). - When I launch AccelDSP, why do I receive "Error: Could not load the syntax highlighting File.invalid command name "AppInfo::Appinfo" while executing "Appinfo::Appinfo ProductDir"? See (Xilinx Answer 30695). - Why does the FFT example design fail the verify RTL step when using ISE Simulator as the HDL Simulator? See (Xilinx Answer 32222). - Why do I receive an error message that "libSecurity.dll" cannot be found when launching AccelDSP? See (Xilinx Answer 32507).