AR# 32645

CPRI v2.1 - Virtex-5 FXT - Missing constraint in Example Design UCF

Description

When when you generate a core for Virtex-5 FXT, there is a period constraint missing in the example design UCF.

Solution

The following constraint should be added to the ucf file: 

 

TIMESPEC "TS_recclk" = PERIOD "recclk_int" 153.6 MHz; 

 

This belongs below the line: 

NET "recclk_int" TNM_NET = "recclk_int";

AR# 32645
Date 05/21/2014
Status Archive
Type General Article