When using the MPMC with a single-data rate (SDR) SDRAM while using ECC, the write data might become shifted or invalid.
How do I resolve this issue?
This issue occurs only when the C_MEM_PART_TRCD parameter time expressed in memory clock cycles, rounded up, is 2 cycles or less.
To work around this issue, increase the C_MEM_PART_TRCD parameter so that the rounded up value is 3 or more clock cycles. This might require changing the C_MEM_PARTNO to a CUSTOM flow so that the parameter can be more easily overridden.
This issue is planned to be fixed with the newest MPMC Core released in EDK 11.3.