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AR# 32705: ISE Simulator (ISim) - ERROR:Simulator:702 - Can not find design test_fifo in library work located at isim/work
ISE Simulator (ISim) - ERROR:Simulator:702 - Can not find design test_fifo in library work located at isim/work
When I run a behavioral simulation in ISim I encounter the following error:
ERROR:Simulator:702 - Can not find design test_fifo in library work located at isim/work
How can I resolve this error?
This error indicates that ISim has not compiled the source file that describes the entity or module in question (in this example, an entity or module called "test_fifo").
To resolve this error, check the following:
Make sure that the VHDL/Verilog source file that describes the missing entity/module has been properly added as a source in the Project Navigator.
Additionally, make sure that the "view association" for this source file has been set to "Simulation" or "All".
If launching ISim in batch mode, make sure that the source file has been properly compiled using vhpcomp/vlogcomp into the work library.
Alternatively, if using the ISim project file (.prj), make sure that the source file is listed in the .prj file.
Check the "Process Properties - Isim Properties" by right clicking on the ISIM and selecting properties.
Then check that the option to "Specify Top Level Instance Name" has the correct testbench specified.
You may need to cleanup the project after modifying this option.
This also occurs when the testbench filename is the same as a schematic filename in the design, for example if TestSplitter.vhd is the testbench but TestSplitter.sch is a schematic file in the design.
When simulation is run the initial step is to convert the TestSplitter.sch file and other schematic files to vhdl.
This appears to cause corruption and results in the TestSplitter.vhd file being removed from the project and the above error being output.
Re-adding the TestSplitter.vhd file to the project and re-running the simulation will fix the problem as the conversion of SCH files to .vhd files is already done.
The best way to avoid this is to ensure that the testbench file has a different name to the schematic files. For example TB_TestSplitter.vhd.