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AR# 32717

XtremeDSP Development Kit-IV ROHS Compliant - Why do I see a reduced SFDR performance on the output of my ADCs, than is described in the XtremeDSP Development Kit-IV User Guide?

Description

Why do I see reduced SFDR performance on the output of my ADCs than is described in the XtremeDSP Development Kit-IV User Guide?

Solution

It was discovered that the drive strength on the I/O driving the ADCs was not strong enough. 

 

This issue should only apply to the XtremeDSP Development Kit-IV RoHS compliant edition. 

 

A new bitstream and source code for the Virtex-II Clock FPGA can be obtained from the Nallatech Support Lounge for the XtremeDSP Development Kit-IV. 

 

http://www.nallatech.com
- See the XtremeDSP Clock Driver Update (May, 8 2009).

AR# 32717
Date Created 06/26/2009
Last Updated 05/23/2014
Status Archive
Type General Article