AR# 32726: 11 EDK - MicroBlaze interrupt does not occur after reset
11 EDK - MicroBlaze interrupt does not occur after reset
If you reset while XMD has stopped MicroBlaze, this causes MicroBlaze to not take interrupts after reset.
When you perform a reset while XMD has stopped MicroBlaze, this causes MicroBlaze to not take interrupts after reset. This is because XMD has disabled interrupts using the debug logic; and this logic is clocked by the JTAG clock, and thus not reset.
The communication between XMD and MicroBlaze is handled through a Debug Control Register (DCR). The DCR supersedes anything that is in MicroBlaze's MSR. If MicroBlaze is stopped in XMD, the only way to get the processor running again is by issuing the "run" or "con" commands in XMD, as the processor is in a stopped state because of values set in the DCR. While the MicroBlaze is in a stopped condition or if XMD is single stepping the processor, interrupts are disabled via the DCR. However, MicroBlaze's MSR will still have the interrupt bit enabled, but the DCR will override the MSR.