For the most recent updates to the IP installation instructions for this core, please go to:
For system requirements:
This file contains release notes for the Xilinx Virtex-6 FPGA GTX Transceiver Wizard v1.2. For the latest core updates, see the product page at:
2. NEW FEATURES
- Implementation support with ChipScope cores for LXT, CXT and SXT families
- For best results, use one of the available protocol templates
3. RESOLVED ISSUES
- New directory structure for the generated example design. Please refer to the Getting Started Guide (UG516) for additional information
- Fixed the issue where additional changes made in the GUI after selecting a protocol template are not reflected in the generated example design
4. KNOWN ISSUES
The following are known issues for v1.2 of this core at time of release:
- This version of the Wizard has limited support for the larger devices with 36 transceivers. The Wizard will only display the lower 24 transceivers on the transceiver selection page.
- To work on around this issue
1. Select transceivers from the available list.
2. Generate the desired wrapper.
3. Manually modify the ucf file to place the transceivers where desired.
- When using RXRECCLK to generate RXUSRCLK/2, it is possible that the design will not meet timing. Please refer to AR 32996 for more information
- RST not held for 3 CLKIN cycles simulation warning. Please see AR 32230 for more information.
- May observe X's and timing simulation failures when doing back annotated simulation when using either the tx_sync deskew module.
- Virtex-6 solutions are pending hardware validation
The most recent information, including known issues, workarounds, and resolutions for this version is provided in the release notes Answer Record for the ISE 11.2 IP Update at:
5. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
6. CORE RELEASE HISTORY
Date By Version Description
06/24/2009 Xilinx, Inc. 1.2 11.2 Release
04/24/2009 Xilinx, Inc. 1.1 Initial release