AR# 32748

Virtex-5 GTX FPGA RocketIO Wizard v1.6 - Release Notes and Known Issues

Description

This Release Notes and Known Issues Answer Record is for the Virtex-5 FPGA GTX RocketIO Wizard v1.6 and contains the following information:

  • New Features
  • Bug Fixes
  • Known Issues

Solution

1) INTRODUCTION


This file contains Release Notes for the Xilinx Virtex-5 FPGA GTX Transceiver Wizard v1.6. For the latest core updates, see the product page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/v5_fpga_gtx_transceiver_wizard.html

2) NEW FEATURES

  • Support for ISE Design Suite 11.2
  • Clock correction sequence length options have been updated. Please refer to (Xilinx Answer 32164) for additional information.
  • Fabric Clock Correction Module. When a 16-bit RX interface is selected with 8b10b decoding, a 1-byte clock correction sequence length is possible only through the use of the new CC_2B_1SKP module.
    When a clock correction sequence length of 1-byte is selected on page 8 of the GUI, the Wizard generates one CC_2B_1SKP module for each GTX Transceiver in a tile.
    Please refer to the "Virtex-5 FPGA RocketIO GTX Transceiver Clock Correction Module" (XTP037) for additional information regarding the module.
  • New directory structure for the generated example design. Please refer to the Getting Started Guide (UG204) for additional information:

https://www.xilinx.com/support/documentation/ip_documentation/v5_gtxwizard_gsg204.pdf

3) KNOWN ISSUES

  • For some of the designs, timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16/20/32/40 bit interface for line rates higher than 2.5 Gb/s.
  • When using RXRECCLK to generate RXUSRCLK/2, it is possible that the design will not meet timing. Please refer to (Xilinx Answer 32996) for more information.
  • RST not held for 3 CLKIN cycles simulation warning. Please see (Xilinx Answer 32230) for more information.
  • Might observe X's and timing simulation failures when doing back annotated simulation if using either the tx_sync deskew module or the fabric clock correction module.
  • For 1-byte Example Design, X's might propagate from the GTX to user logic.
  • Simulation warning related to the FIFO used in the external Clock Correction module. Please see (Xilinx Answer 33925) for more information.
  • It is very difficult for the external Clock Correction module to meet timing at line rates above 5Gb/s and has not been verified to operate above that rate.
    At rates greater than 5Gb/s, the operation of this module is not guaranteed or supported.

The most recent information, including known issues, work-arounds, and resolutions for this version is provided in the Release Notes Answer Record for the ISE Design Suite 11.2 IP Update at:

https://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf


4) CORE RELEASE HISTORY

Date By Version Description

================================================================================

06/24/2009 Xilinx, Inc. 1.6 ISE 11.2 Release, Fabric Clock Correction module

09/18/2008 Xilinx, Inc. 1.5 TXT support, Lane-to-lane Deskew module

06/27/2008 Xilinx, Inc. 1.4 OBSAI, PCIe Gen2, OOBDETECT_THRESHOLD update

04/25/2008 Xilinx, Inc. 1.3 Optimized CDR attributes

03/24/2008 Xilinx, Inc. 1.2 Initial release

================================================================================

AR# 32748
Date 07/03/2017
Status Active
Type General Article
Devices
IP